SH7710 Datasheet, PDF (687/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.2 EtherC Mode Register (ECMR)
ECMR is a 32-bit readable/writable register and specifies the operating mode of the Ethernet
controller. The settings in this register are normally made in the initialization process following a
reset.
The operating mode setting must not be changed while the transmitting and receiving functions
are enabled. To switch the operating mode, return the EtherC and E-DMAC to their initial states
by means of the SWR bit in EDMR before making settings again.
Initial
Bit
Bit Name Value
31 to 14 
All 0
13
MCT
0
12
PRCEF 0
11

0
10

0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Multicast Address Frame Receive Mode
0: Frames other than the multicast address set by the
CAM entry table 0 to 31 (H/L) registers are
received. However, if the on-chip CAM entry table
reference is disabled, all multicast address frames
are received.
1: Only the multicast address set by the CAM entry
table 0 to 31 (H/L) registers is received.
R/W CRC Error Frame Reception Enable
0: A receive frame including a CRC error is received
as a frame with an error.
1: A receive frame including a CRC error is received
as a frame without an error.
When this bit is cleared to 0, the CRC error is
reflected in ECSR of the E-DMAC and the status of
the receive descriptor. When this bit is set to 1, a
frame is received as a normal frame.
R
Reserved
R
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Dec. 07, 2005 Page 645 of 950
REJ09B0079-0200