SH7710 Datasheet, PDF (755/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
Table 18.3 Reception Frame Process
CAM Entry Table
Referencing Results Frame
Normal Mode
MCT = 0
MCT = 1
Promiscuous Mode
MCT = 0
MCT = 1
CAM hit
Frame to this LSI Discarded
Discarded
(when addresses
match)
Broadcast frame
Multicast frame
Discarded
Discarded
Received
Discarded
Discarded
Received
Frames to
destinations other
than this LSI
Received
Discarded
CAM mishit
Frames to this LSI Received
Received
(when addresses do Broadcast frame
not match)
Multicast frame
Received
Received
Discarded
Received
Received
Discarded
Frames to
destinations other
than this LSI
Discarded
Received
[Legend]
MCT (Bit 13 in ECMR): Multicast receive mode (0: Receive when CAM mishit/
1: Receive when CAM hit)
Table 18.4 Relay Frame Process (With CAM)
Frame
Relay Function Setting
Register Bit
CAM Hit
CAM Mishit
Multicast frame
FW40/1 = 0
Relayed
Discarded
FW40/1 = 1
Discarded
Relayed
Frames to destinations other FW40/1 = 0
than this LSI
FW40/1 = 1
Relayed
Discarded
Discarded
Relayed
Note: CAM can be referenced only for multicast frames and frames to destinations other than this
LSI. The processing of frames to this LSI and broadcast frames conforms to the values of
the relay function setting register regardless of CAM reference.
When External CAM Logic is Used: In addition to the on-chip CAM entry table, use of the
CAMSEN0 and CAMSEN1 pins allows referencing of evaluation results of the external CAM
logic connected externally to this LSI for frame processing evaluation. This function externally
connects the CAM logic for comparing the destination address in receive frames, and receives the
results of comparing destination addresses corresponding to the signals (RXD3 to RXD0) input
from the MII to determine whether to receive or discard the corresponding frame. Figure 18.5
Rev. 2.00 Dec. 07, 2005 Page 713 of 950
REJ09B0079-0200