SH7710 Datasheet, PDF (832/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 22 I/O Ports
Table 22.1 Port A Data Register (PADR) Read/Write Operations
PAnMD1 PAnMD0 Pin State
Read
0
0
Other function PADR value
1
1
0
1
[Legend]
n = 0 to 7
Output
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
PADR value
Pin state
Pin state
Write
Value is written to PADR, but does not
affect pin state.
Write value is output from pin.
Value is written to PADR, but does not
affect pin state.
Value is written to PADR, but does not
affect pin state.
22.2.2 Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores the data for pins PTB7 to PTB0. Bits
PB7DT to PB0DT correspond to the pins PTB7 to PTB0. PBDR is initialized to H′00 by a power-
on reset but is not initialized by a manual reset, in standby mode, or sleep mode.
Initial
Bit Bit Name Value
7
PB7DT
0
6
PB6DT
0
5
PB5DT
0
4
PB4DT
0
3
PB3DT
0
2
PB2DT
0
1
PB1DT
0
0
PB0DT
0
R/W Description
R/W
When the pin function is general output port, if the port
R/W
is read, the value of the corresponding PBDR bit is
returned directly. When the function is general input
R/W
port, if the port is read, the corresponding pin level is
R/W
read. Tables 22.2 and 22.3 show the function of
PBDR.
R/W
R/W
R/W
R/W
Rev. 2.00 Dec. 07, 2005 Page 790 of 950
REJ09B0079-0200