SH7710 Datasheet, PDF (910/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 25 Electrical Characteristics
25.3.3 AC Bus Timing
Table 25.7 Bus Timing (1)
(Conditions: V_CCQ = V_CCQ-RTC = 3.0 to 3.6 V, V_CC = V_CC-PLL1 = V_CC-PLL2 = 1.4 to 1.6 V,
V Q = V = V Q-RTC = V -PLL1 = V -PLL2 = 0 V, T = –20 to 75°C, clock mode 0/1/2/4/5/6/7)
SS
SS
SS
SS
SS
a
66.67 MHz
Item
Symbol Min.
Max.
Unit Figure
Address delay time 1
t
1
AD1
Address delay time 2
t_AD2
—
Address setup time
t_AS
0
Address hold time
t
0
AH
BS delay time
t
—
BSD
CS delay time 1
t
1
CSD1
Read/write delay time 1 t_RWD1
1
Read strobe delay time t
—
RSD
12
ns
1/2 t_cyc+12
—
—
10
10
10
1/2 t +10
cyc
25.17 to 25.42
25.21
25.17 to 25.20
25.17 to 25.35, 25.39 to
25.42
25.17 to 25.42
25.17 to 25.21, 25.39 to
25.40
Read data setup time 1 t_RDS1
1/2 t_cyc+6 —
25.17 to 25.20, 25.39 to
25.42
Read data setup time 2 t
6
—
RDS2
25.22 to 25.25, 25.30 to
25.32
Read data setup time 3 t
RDS3
Read data hold time 1 t
RDH1
1/2 t +6 —
cyc
0
—
25.21
25.17 to 25.20, 25.39 to
25.42
Read data hold time 2 t
2
—
RDH2
25.22 to 25.25, 25.30 to
25.32
Read data hold time 3
t_RDH3
0
Write enable delay time t_WED
—
—
1/2 t_cyc+10
25.21
25.17 to 25.21, 25.39 to
25.40
Write data delay time 1 t
—
12
WDD1
25.17 to 25.20, 25.39 to
25.42
Write data delay time 2 t
—
12
WDD2
25.26 to 25.29, 25.33 to
25.35
Write data hold time 1 t
1
—
WDH1
Write data hold time 2
t_WDH2
1
—
25.17 to 25.20
25.26 to 25.29, 25.33 to
25.35
Rev. 2.00 Dec. 07, 2005 Page 868 of 950
REJ09B0079-0200