SH7710 Datasheet, PDF (241/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Memory Management Unit (MMU)
Table 5.1 Access States Designated by D, C, and PR Bits
Privileged Mode
Reading
Writing
D bit 0 Permitted
Initial page write
exception
1 Permitted
Permitted
C bit 0 Permitted
(no caching)
Permitted
(no caching)
1 Permitted
Permitted
(with caching) (with caching)
PR bit 00 Permitted
TLB protection
violation
exception
01 Permitted
Permitted
10 Permitted
11 Permitted
TLB protection
violation
exception
Permitted
User Mode
Reading
Writing
Permitted
Initial page write
exception
Permitted
Permitted
Permitted
(no caching)
Permitted
(no caching)
Permitted
(with caching)
Permitted
(with caching)
TLB protection
violation
exception
TLB protection
violation
exception
TLB protection
violation
exception
TLB protection
violation
exception
Permitted
TLB protection
violation
exception
Permitted
Permitted
Rev. 2.00 Dec. 07, 2005 Page 199 of 950
REJ09B0079-0200