SH7710 Datasheet, PDF (838/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 23 User Debugging Interface (H-UDI)
Bit
15 to 13
12
11 to 8
Bit Name
TI7 to TI5
TI4
TI3 to TI0
Initial
Value
All 1
0
All 1
7 to 2 
All 1
1

0
0

1
R/W Description
R
Test Instruction 7 to 0
R
The H-UDI instruction is transferred to SDIR by a
R
serial input from TDI.
For commands, see table 23.2.
R
Reserved
These bits are always read as 1.
R
Reserved
This bit is always read as 0.
R
Reserved
This bit is always read as 1.
Table 23.2 H-UDI Commands
Bits 15 to 8
TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0
Description
0
0
0
0
—
—
—
—
JTAG EXTEST
0
0
1
0
—
—
—
—
JTAG CLAMP
0
0
1
1
—
—
—
—
JTAG HIGHZ
0
1
0
0
—
—
—
—
JTAG SAMPLE/PRELOAD
0
1
1
0
—
—
—
—
H-UDI reset negate
0
1
1
1
—
—
—
—
H-UDI reset assert
1
0
1
—
—
—
—
—
H-UDI interrupt
1
1
1
0
—
—
—
—
JTAG IDCODE (Initial value)
1
1
1
1
—
—
—
—
JTAG BYPASS
Other than the above
Reserved
23.3.3 Boundary Scan Register (SDBSR)
SDBSR is a shift register, located on the PAD, for controlling the input/output pins of this LSI.
The initial value is undefined. SDBSR cannot be accessed by the CPU.
Using the EXTEST, SAMPLE/PRELOAD, CLAMP, and HIGHZ commands, a boundary scan
test conforming to the JTAG standard can be carried out. Table 23.3 shows the correspondence
between this LSI’s pins and boundary scan register bits.
Rev. 2.00 Dec. 07, 2005 Page 796 of 950
REJ09B0079-0200