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| SH7710 Datasheet, PDF (888/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series | |||
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Section 24 List of Registers
24.3 Register States in Each Operating Mode
Register
Abbreviation
INTEVT
INTEVT2
TRA
EXPEVT
TEA
MMUCR
PTEH
PTEL
TTB
CCR1
CCR2
CCR3
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
IPRI
ICR0
ICR1
IRR0
IRR1
IRR2
IRR3
IRR4
Power-on
Reset*1
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Manual
Reset*1
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Software
standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Module
Standby





Retained
Retained
Retained
Retained
Retained
Retained
Retained
















Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Module
Exception
handling
MMU
Cache
INTC
Rev. 2.00 Dec. 07, 2005 Page 846 of 950
REJ09B0079-0200
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