SH7710 Datasheet, PDF (18/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

11.7.1 Watchdog Timer Counter (WTCNT).................................................................... 324
11.7.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 324
11.7.3 Notes on Register Access ..................................................................................... 326
11.8 Using WDT........................................................................................................................ 327
11.8.1 Canceling Standbys .............................................................................................. 327
11.8.2 Changing Frequency ............................................................................................. 328
11.8.3 Using Watchdog Timer Mode .............................................................................. 328
11.8.4 Using Interval Timer Mode .................................................................................. 328
11.9 Notes on Board Design ...................................................................................................... 329
Section 12 Bus State Controller (BSC) ............................................................. 331
12.1 Features.............................................................................................................................. 331
12.2 Input/Output Pins............................................................................................................... 334
12.3 Area Overview................................................................................................................... 336
12.3.1 Area Division........................................................................................................ 336
12.3.2 Shadow Area......................................................................................................... 336
12.3.3 Address Map......................................................................................................... 338
12.3.4 Area 0 Memory Type and Memory Bus Width .................................................... 340
12.3.5 Data Alignment..................................................................................................... 340
12.4 Register Descriptions......................................................................................................... 341
12.4.1 Common Control Register (CMNCR) .................................................................. 342
12.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) ..... 345
12.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)... 350
12.4.4 SDRAM Control Register (SDCR)....................................................................... 377
12.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 380
12.4.6 Refresh Timer Counter (RTCNT)......................................................................... 381
12.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 382
12.5 Operation ........................................................................................................................... 383
12.5.1 Endian/Access Size and Data Alignment.............................................................. 383
12.5.2 Normal Space Interface ........................................................................................ 389
12.5.3 Access Wait Control ............................................................................................. 395
12.5.4 CSn Assert Period Expansion ............................................................................... 397
12.5.5 SDRAM Interface ................................................................................................. 398
12.5.6 Burst ROM (Clock Asynchronous) Interface ....................................................... 439
12.5.7 Byte-Selection SRAM Interface ........................................................................... 441
12.5.8 PCMCIA Interface................................................................................................ 446
12.5.9 Burst ROM (Clock Synchronous) Interface.......................................................... 452
12.5.10 Wait between Access Cycles ................................................................................ 453
12.5.11 Bus Arbitration ..................................................................................................... 453
12.5.12 Others.................................................................................................................... 457
Rev. 2.00 Dec. 07, 2005 Page xviii of xlii