SH7710 Datasheet, PDF (803/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Ethernet frame is received. In such a case, the received Ethernet frame is transferred sequentially
to buffers, 500 bytes for each buffer, starting with the first descriptor. Only the last 14 bytes are
transferred to the fourth buffer. When a frame longer than RBL of a descriptor is received, the
E-DMAC transfers the remaining data to the receive buffer by using the subsequent descriptors.
As an example of efficient single-frame/multi-buffer operation, information items on different
processing layers in an Ethernet frame can be separated from each other by using different buffers.
For example, the destination address, transmit source address, and type field data in an Ethernet
frame can be stored in buffer 1 (with RBL set to 14 bytes) and the remaining data can be stored in
buffer 2 (with RBL set to 1500 bytes). All receive frames, of course, can be stored in a single
buffer if multiple descriptors are prepared and RBL of each descriptor is set to more than 1514
bytes (maximum Ethernet frame length).
Receive descriptor
31 30 29 28 27 26
0
R RR RR
RD0 ^{A D F F F}
C LP PE
RFS26 to RFS0
TE1 0
RBL
15
0
RD1
31
16
RDL
31
0
RD2
RBA
Padding (4/20/52 bytes)*
Receive buffer
Valid receive data
Note: * According to the descriptor length set by the DL0 and DL1 bits in EDMR, the padding size is determined as follows:
For 16 bytes: Padding = 4 bytes
For 32 bytes: Padding = 20 bytes
For 64 bytes: Padding = 52 bytes
Figure 19.3 Relationship between Receive Descriptor and Receive Buffer
Rev. 2.00 Dec. 07, 2005 Page 761 of 950
REJ09B0079-0200