SH7710 Datasheet, PDF (976/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
• CS3WCR
Page Revision (See Manual for Details)
368
Bit
14
13
11
10
Bit
Name Description
TRP1
TRP0
Number of Wait Cycles Waiting Completion of
Precharge Specify the number of minimum wait
cycles to be inserted to wait the completion of
precharge. The setting for areas 2 and 3 is
common.
(1) From starting auto-charge to issuing the ACTV
command for the same bank
(2) From issuing the PRE/PALL command to
issuing the ACTV command for the same
bank
(3) To transiting to power-down mode/deep
power-down mode
(4) From issuing the PALL command at auto-
refresh to issuing the REF command
(5) From issuing the PALL command at self-
refresh to issuing the SELF command
00: 0 cycle
01: 1 cycles
10: 2 cycles
11: 3 cycles
TRCD1 Number of Wait Cycles from ACTV Command to
TRCD0 ^{READ (A)/WRIT (A) Command}
Specify the number of minimum wait cycles from
issuing the ACTV command to issuing the READ
(A)/WRIT (A) command. The setting for areas 2
and 3 is common.
00: 0 cycle (no wait cycle)
01: 1 cycle
10: 2 cycles
11: 3 cycles
Rev. 2.00 Dec. 07, 2005 Page 934 of 950
REJ09B0079-0200