SH7710 Datasheet, PDF (213/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H′0A0
An exception occurred during write: H′0C0
• Remarks
The logical address (32 bits) that caused the exception is set in TEA and the MMU registers
are updated.
Initial page write exception:
• Conditions
A hit occurred to the TLB for a data write access, but D = 0.
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
H′080
• Remarks
The logical address (32 bits) that caused the exception is set in TEA and the MMU registers
are updated.
Rev. 2.00 Dec. 07, 2005 Page 171 of 950
REJ09B0079-0200