SH7710 Datasheet, PDF (49/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview and Pin Function
1.2 Block Diagram
SuperH
CPU core
DSP core
User break
controller
(UBC)
Advanced
user
debugger
(AUD)
L bus
CPU bus (I clock)
X/Y memory
Instructions/data for
CPU/DSP 16 kbytes
X bus
Y bus
Cache
access
controller
(CCN)
Internal bus (B clock)
Cache
memory
32 kbytes
Memory
management
unit
(MMU)
Bus state
controller
(BSC)
IP security
accelerator
(IPSEC)
Peripheral
bus
controller
External bus
Direct
memory
access
controller
(DMAC)
Ethernet
controller
direct memory
access
controller
(E-DMAC)
Transmit FIFO
(2 kbytes)
Ethernet controller 0
Receive FIFO
(EtherC0)
Ethernet 0
(2 kbytes)
Transfer FIFO Transfer FIFO
(3 kbytes)
(3 kbytes)
Transmit FIFO
(2 kbytes)
Receive FIFO
(2 kbytes)
Ethernet controller 1
(EtherC1)
Ethernet 1
Peripheral bus (P clock)
128-byte
SRAM
Serial I/O
with FIFO
(SIOF)*
Serial
communication
interface
with FIFO
(SCIF)*
User
debugging
interface
(H-UDI)
Interrupt
controller
(INTC)
Realtime
clock
(RTC)
Timer
unit
(TMU)
On-chip
oscillation
circuits
(CPG)
(WDT)
Note: * SCIF and SIOF have two channels respectively.
Figure 1.1 Block Diagram
Rev. 2.00 Dec. 07, 2005 Page 7 of 950
REJ09B0079-0200