SH7710 Datasheet, PDF (664/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
• FIFO transmit request: TDREQ (transmit interrupt source)
• FIFO receive request: RDREQ (receive interrupt source)
The request conditions for FIFO transmit or receive can be specified individually. The request
conditions for the FIFO transmit and receive are specified by the TFWM2 to TFWM0 bits and
RFWM2 to RFWM0 bits in SIFCTR, respectively. Tables 17.8 and 17.9 summarize the conditions
specified by SIFCTR.
Table 17.8 Conditions to Issue Transmit Request
TFWM2 to TFWM0
000
100
101
110
111
Number of
Requested Stages
1
4
8
12
16
Transmit Request
Used Areas
Empty area is 16 stages
Smallest
Empty area is 12 stages or more
Empty area is 8 stages or more
Empty area is 4 stages or more
Empty area is 1 stage or more Largest
Table 17.9 Conditions to Issue Receive Request
RFWM2 to RFWM0
000
100
101
110
111
Number of
Requested Stages
1
4
8
12
16
Receive Request
Valid data is 1 stage or more
Valid data is 4 stages or more
Valid data is 8 stages or more
Valid data is 12 stages or more
Valid data is 16 stages
Used Areas
Smallest
Largest
The number of stages of the FIFO is always sixteen even if the data area or empty area exceeds the
above stage number. Accordingly, an overrun error or underrun error occurs if data area or empty
area exceeds sixteen FIFO stages. FIFO transmission or reception request is cancelled when the
above condition is not satisfied even if the FIFO is not empty or full.
Number of FIFOs: The number of FIFO stages used in transmission and reception is indicated by
the following register.
• Transmit FIFO: The number of empty FIFO stages are indicated by the TFUA4 to TFUA0 bits
in SIFCTR.
Rev. 2.00 Dec. 07, 2005 Page 622 of 950
REJ09B0079-0200