SH7710 Datasheet, PDF (387/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
12.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
CSnBCR specifies the type of memory connected to each space, data-bus width of each space, and
the number of wait cycles between access cycles.
Do not access external memory other than area 0 until the CSnBCR initialization is completed.
Initial
Bit
Bit Name Value R/W Description
31

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
30
IWW2
0
29
IWW1
1
28
IWW0
1
R/W Idle Cycles between Write-Read Cycles and Write-Write
R/W ^Cycles
R/W ^{These bits specify the number of idle cycles to be inserted}
after the access to a memory that is connected to the
space. The target access cycles are the write-read cycle
and write-write cycle.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Rev. 2.00 Dec. 07, 2005 Page 345 of 950
REJ09B0079-0200