SH7710 Datasheet, PDF (974/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
11.9 Notes on Board Design
Bypass Capacitors:
Section 12 Bus State Controller
(BSC)
12.4 Register Descriptions
Page Revision (See Manual for Details)
329 Pin assignments of HQFP2828-256 (FP-256G/GV)
Vss/VssQ and Vcc/VccQ pair of digital circuitry
:
Vss/VssQ and Vcc/VccQ pair of the on-chip
oscillator
193 and 196, 251 and 252, 253 and 254
Pin assignments of P-LFGA1717-256 (BP-256H/HV)
Vss/VssQ and Vcc/VccQ pair of digital circuitry
D2-B1, E1-F4, G2-G3, J2-J4, L3-L2, N3-N2, R4-P2,
U2-W1, V4-Y4, Y6-U7, W8-V8, V10-W10, V11-W11,
V13-W13, U15-W14, W17-Y19, U18-U20, P17-N19,
N18-P20, L17-L20, J18-J19, E20-E17, D19-B20,
C19-A20, D15-B14, C14-A15, B11-D11, C10-B10,
C8-B8, D6-B7
Vss/VssQ and Vcc/VccQ pair of the on-chip
oscillator
B19-A19, C3-B5, and C5-C4
341 • Refresh timer control/status register (RTCSR)*¹
• Refresh timer counter (RTCNT)*¹
• Refresh time constant register (RTCOR)*¹
• SDRAM mode register for area 2 (SDMR2)*²
• SDRAM mode register for area 3 (SDMR3)*²
Notes: 1. This register only accepts 32-bit writing to
prevent incorrect writing. In this case, the
upper 16 bits of the data must be H'A55A.
Otherwise, writing cannot be performed. In
reading, the upper 16 bits are read as
H'0000.
2. The contents of this register are
stored in SDRAM. When this register space
is accessed, the corresponding register in
SDRAM is written to. For details, see
description of Power-on Sequence in section
12.5.5, SDRAM Interface.
Rev. 2.00 Dec. 07, 2005 Page 932 of 950
REJ09B0079-0200