SH7710 Datasheet, PDF (281/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by the IRL interrupt
handling.
Interrupt
request
Priority
encoder
4
IRL3 to IRL0
SH7710
IRL3 to IRL0
Figure 8.2 Example of IRL Interrupt Connection
8.3.4 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following 14 modules:
• Direct memory access controller (DMAC)
• Serial communication interface with FIFO (SCIF0 and SCIF1)
• Direct memory access controller for ethernet controller (E-DMAC)
(includes an EtherC interrupt)
• IP security accelerator (IPSEC)
• Serial I/O with FIFO (SIOF0 and SIOF1)
• Timer unit (TMU0 to TMU2)
• Realtime clock (RTC)
• Watchdog timer (WDT)
• Bus state controller (BSC)
• User-debugging interface (H-UDI)
Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the
interrupt event registers (INTEVT and INTEVT2). It is easy to identify sources by using the value
of INTEVT or INTEVT2 as a branch offset.
A priority level (from 0 to 15) can be set for each module except the H-UDI by writing to the
interrupt priority registers A, B, and E to I (IPRA, IPRB, and IPRE to IPRI). The priority level of
the H-UDI interrupt is 15 (fixed).
Rev. 2.00 Dec. 07, 2005 Page 239 of 950
REJ09B0079-0200