SH7710 Datasheet, PDF (320/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
9.2.10 Execution Times Break Register (BETR)
BETR is a 16-bit readable/writable register. When the execution-times break condition of channel
B is enabled, this register specifies the number of execution times to make the break. The
maximum number is 2¹² – 1 times. When a break condition is satisfied, it decreases BETR. A
break is issued when the break condition is satisfied after BETR becomes H'0001.
Initial
Bit
Bit Name Value R/W Description
15 to 12 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
11 to 0 BET11 to All 0 R/W Number of Execution Times
BET0
Note: When the instruction fetch cycle is specified as the break condition of the channel B, and its
break condition is triggered by the following instructions, the BETR is decremented by the
following value (not by one).
Instruction
RTE
DMULS.L Rm,Rn
DMULU.L Rm,Rn
MAC.L @Rm+,@Rn
MAC.W @Rm+,@Rn
MUL.L Rm,Rn
AND.B #imm,@(R0,GBR)
OR.B #imm,@(R0,GBR)
TAS.B @Rn
TST.B #imm,@(R0,GBR)
XOR.B #imm,@(R0,GBR)
LDC Rm,SR
LDC Rm,GBR
LDC Rm,VBR
LDC Rm,SSR
LDC Rm,SPC
LDC Rm,R0_BANK
LDC Rm,R1_BANK
LDC Rm,R2_BANK
LDC Rm,R3_BANK
LDC Rm,R4_BANK
LDC Rm,R5_BANK
LDC Rm,R6_BANK
LDC Rm,R7_BANK
Decrement value
4
2
2
2
2
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
Instruction
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDC.L @Rm+,SSR
LDC.L @Rm+,SPC
LDC.L @Rm+,R0_BANK
LDC.L @Rm+,R1_BANK
LDC.L @Rm+,R2_BANK
LDC.L @Rm+,R3_BANK
LDC.L @Rm+,R4_BANK
LDC.L @Rm+,R5_BANK
LDC.L @Rm+,R6_BANK
LDC.L @Rm+,R7_BANK
LDC.L @Rn+,MOD
LDC.L @Rn+,RS
LDC.L @Rn+,RE
LDC Rn,MOD
LDC Rn,RS
LDC Rn,RE
BSR label
BSRF Rm
JSR @Rm
Decrement value
6
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2
Rev. 2.00 Dec. 07, 2005 Page 278 of 950
REJ09B0079-0200