SH7710 Datasheet, PDF (896/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 List of Registers
Register
Power-on Manual
Abbreviation Reset*¹
Reset*¹
Software
standby
Module
Standby
Sleep
Module
TBRARn
(n = 0, 1)
Initialized Initialized Retained 
Retained E-DMAC
TDFARn
(n = 0, 1)
Initialized Initialized Retained 
Retained
FCFTRn
(n = 0, 1)
Initialized Initialized Retained 
Retained
TRIMDn
(n = 0, 1)
Initialized Initialized Retained 
Retained
PACR
Initialized Retained Retained 
Retained PFC
PBCR
Initialized Retained Retained 
Retained
PCCR
Initialized Retained Retained 
Retained
PETCR
Initialized Retained Retained 
Retained
PADR
Initialized Retained Retained 
Retained I/O port
PBDR
Initialized Retained Retained 
Retained
PCDR
Initialized Retained Retained 
Retained
SDIR
Retained Retained Retained Retained Retained H-UDI
SDID/SDIDH Retained Retained Retained Retained Retained
SDIDL
Retained Retained Retained Retained Retained
Notes: 1. For the initial values of each register, see the sections for the corresponding modules. If
the initial value is undefined, it is shown as initialized since the data is not retained.
2. Some bits are initialized in standby mode. See section 8, Interrupt Controller (INTC), for
details.
3. If the multiplication rate of PLL1 is modified, this register is initialized.
4. Some bits are initialized by a power-on reset. See section 15, Realtime Clock (RTC), for
details.
5. Some bits are initialized by a manual reset. See section 15, Realtime Clock (RTC), for
details.
Rev. 2.00 Dec. 07, 2005 Page 854 of 950
REJ09B0079-0200