SH7710 Datasheet, PDF (686/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.1 Software Reset Register (ARSTR)
ARSTR resets all modules (EtherC and E-DMAC) related to the Ethernet. By writing 1 to the
ARST bit in ARSTR, a software reset is issued to all modules related to the Ethernet (for 64 cycles
at external bus clock Bφ). The ARST bit is always read as 0. While a software reset is issued,
register access to all modules related to the Ethernet is prohibited.
Bit
31 to 1
Initial
Bit Name Value

All 0
0
ARST
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Software Reset
When written with 1, a software reset is issued to all
modules related to the Ethernet (for 64 cycles at
external bus clock Bφ).
Writing 0 does not affect this bit. This bit is always read
as 0.
While a software reset is issued, register access to all
modules related to the Ethernet is prohibited. The
following registers are not initialized by a software
reset.
TSU_ADRH0 to TSU_ADRH31, TSU_ADRL0 to
TSU_ADRL31, TXNLCR0, TXNLCR1, TXALCR0,
TXALCR1, RXNLCR0, RXNLCR1, RXALCR0,
RXALCR1, FWNLCR0, FWNLCR1, FWALCR0,
FWALCR1
Rev. 2.00 Dec. 07, 2005 Page 644 of 950
REJ09B0079-0200