SH7710 Datasheet, PDF (696/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.11 Delayed Collision Detect Counter Register (CDCR)
CDCR is a 32-bit counter that indicates the number of all delayed collisions that accured on the
line after the start of data transmission. When the value in this register reaches H'FFFFFFFF,
count-up is halted. The counter value is cleared to 0 by a write to this register with any value.
Initial
Bit
Bit Name Value
31 to 0 COSDC31 All 0
to
COSDC0
R/W Description
R/W Delayed Collision Detect Count
These bits indicate the number of all delayed collisions
after the start of data transmission.
18.3.12 Lost Carrier Counter Register (LCCR)
LCCR is a 32-bit counter that indicates the number of times the carrier was lost during data
transmission. When the value in this register reaches H'FFFFFFFF, the count is halted. The
counter value is cleared to 0 by writing to this register with any value.
Initial
Bit
Bit Name Value
31 to 0 LCC31 to All 0
LCC0
R/W Description
R/W Lost Carrier Count
These bits indicate the number of times the carrier was
lost during data transmission.
18.3.13 Carrier Not Detect Counter Register (CNDCR)
CNDCR is a 32-bit counter that indicates the number of times the carrier could not be detected
while the preamble was being sent. When the value in this register reaches H'FFFFFFFF, the count
is halted. The counter value is cleared to 0 by a write to this register with any value.
Initial
Bit
Bit Name Value
31 to 0 CNDC31 All 0
to CNDC0
R/W Description
R/W Carrier Not Detect Count
These bits indicate the number of times the carrier
was not detected.
Rev. 2.00 Dec. 07, 2005 Page 654 of 950
REJ09B0079-0200