SH7710 Datasheet, PDF (183/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Instruction
Instruction Code Operation
Execution
States T Bit
LDS.L @Rn + ,Y0 0100nnnn10100110 (Rn) →Y0, Rn + 4→Rn 1

LDS.L @Rn + ,Y1 0100nnnn10110110 (Rn) →Y1, Rn + 4→Rn 1

LDC.L @Rn + ,MOD 0100nnnn01010111 (Rn) →MOD, Rn + 4→Rn 4

LDC.L @Rn + ,RS 0100nnnn01100111 (Rn) →RS, Rn + 4→Rn 4

LDC.L @Rn + ,RE 0100nnnn01110111 (Rn) →RE, Rn + 4→Rn 4

LDS Rn,DSR
0100nnnn01101010 Rn→DSR
1

LDS Rn,A0
0100nnnn01111010 Rn→A0
1

LDS Rn,X0
0100nnnn10001010 Rn→X0
1

LDS Rn,X1
0100nnnn10011010 Rn→X1
1

LDS Rn,Y0
0100nnnn10101010 Rn→Y0
1

LDS Rn,Y1
0100nnnn10111010 Rn→Y1
1

LDC Rn,MOD
0100nnnn01011110 Rn→MOD
4

LDC Rn,RS
0100nnnn01101110 Rn→RS
4

LDC Rn,RE
0100nnnn01111110 Rn→RE
4

Category
Rev. 2.00 Dec. 07, 2005 Page 141 of 950
REJ09B0079-0200