SH7710 Datasheet, PDF (355/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 11 On-Chip Oscillation Circuits
11.2 Overview of CPG
11.2.1 CPG Block Diagram
A block diagram of the on-chip clock pulse generator is shown in figure 11.1.
CKIO
CKIO2
Clock pulse generator
PLL circuit 1
(× 1, 2, 3)
Divider 1
×1
× 1/2
× 1/3
× 1/4
× 1/6
Internal clock
(Iφ)
XTAL
EXTAL
Crystal
oscillator
PLL circuit 2
(× 1, 2, 4)
CPG control unit
Clock frequency
control circuit
FRQCR
Bus clock
(Bφ=CKIO)
Peripheral clock
(Pφ)
Standby control
circuit
STBCR STBCR2 STBCR3
Bus interface
Internal bus
[Legend]
FRQCR: Frequency control register
STBCR: Standby control register
STBCR2: Standby control register 2
STBCR3: Standby control register 3
Figure 11.1 Block Diagram of CPG
Rev. 2.00 Dec. 07, 2005 Page 313 of 950
REJ09B0079-0200