SH7710 Datasheet, PDF (343/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Power-Down Modes
Bit
Bit Name Initial Value R/W Description
2
MSTP5 0
R/W Module Stop Bit 5
When the MSTP5 bit is set to 1, the supply of the
clock to the cache memory is halted.
0: The cache memory runs
1: Clock supply to the cache memory halted
1

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
0
MSTP3 0
R/W Module Stop Bit 3
When the MSTP3 bit is set to 1, the supply of the
clock to the X/Y memory is halted.
0: The X/Y memory runs
1: Clock supply to the X/Y memory halted
10.2.3 Standby Control Register 3 (STBCR3)
STBCR3 is an 8-bit readable/writable register that controls the operation of the peripheral modules
in the power-down mode. This register is initialized to H′00 at power-on reset but retains the
previous value after manual reset.
Bit
7
6 to 4
3
Bit Name Initial Value R/W
MSTP37 0
R/W

All 0
R
MSTP33 0
R/W
Description
Module Stop Bit 37
When the MSTP37 bit is set to 1, the supply of the
clock to the IPSEC is halted.
0: IPSEC runs
1: Clock supply to IPSEC halted
Reserved
These bits are always read as 0. The write value
should always be 0.
Module Stop Bit 33
When the MSTP33 bit is set to 1, the supply of the
clock to the SIOF1 is halted.
0: SIOF1 runs
1: Clock supply to SIOF1 halted
Rev. 2.00 Dec. 07, 2005 Page 301 of 950
REJ09B0079-0200