SH7710 Datasheet, PDF (632/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
17.3 Register Descriptions
The SIOF has the following registers. For the addresses and access size of these registers, refer to
section 24, List of Registers.
1. Channel 0
• SIOF mode register_0 (SIMDR_0)
• Serial clock select register_0 (SISCR_0)
• Serial transmit data assign register_0 (SITDAR_0)
• Serial receive data assign register_0 (SIRDAR_0)
• Serial control data assign register_0 (SICDAR_0)
• SIOF control register_0 (SICTR_0)
• SIOF FIFO control register_0 (SIFCTR_0)
• SIOF status register_0 (SISTR_0)
• SIOF interrupt enable register_0 (SIIER_0)
• Serial transmit data register_0 (SITDR_0)
• Serial receive data register_0 (SIRDR_0)
• Serial transmit control data register_0 (SITCR_0)
• Serial receive control data register_0 (SIRCR_0)
2. Channel 1
• SIOF mode register_1 (SIMDR_1)
• Serial clock select register_1 (SISCR_1)
• Serial transmit data assign register_1 (SITDAR_1)
• Serial receive data assign register_1 (SIRDAR_1)
• Serial control data assign register_1 (SICDAR_1)
• SIOF control register_1 (SICTR_1)
• SIOF FIFO control register_1 (SIFCTR_1)
• SIOF status register_1 (SISTR_1)
• SIOF interrupt enable register_1 (SIIER_1)
• Serial transmit data register_1 (SITDR_1)
• Serial receive data register_1 (SIRDR_1)
• Serial transmit control data register_1 (SITCR_1)
• Serial receive control data register_1 (SIRCR_1)
Rev. 2.00 Dec. 07, 2005 Page 590 of 950
REJ09B0079-0200