SH7710 Datasheet, PDF (791/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.2.13 E-DMAC Operation Control Register (EDOCR)
EDOCR is a 32-bit readable/writable register that specifies the control methods used in E-DMAC
operation.
Initial
Bit
Bit Name Value R/W Description
31 to 4 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
3
FEC
0
R/W FIFO Error Control
Specifies E-DMAC operation when transmit FIFO
underflow or receive FIFO overflow occurs.
0: E-DMAC operation continues when underflow or
overflow occurs
1: E-DMAC operation halts when underflow or
overflow occurs
2
AEC
0
R/W Address Error Control
Indicates detection of an illegal memory address in
an attempted E-DMAC transfer.
0: Illegal memory address not detected (normal
operation)
1: Indicates that E-DMAC operation is halted because
an illegal memory address is detected. When 0 is
written to this bit, the E-DMAC resumes operation
1 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Dec. 07, 2005 Page 749 of 950
REJ09B0079-0200