SH7710 Datasheet, PDF (169/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

39 31
S Source 1
0
Section 3 DSP Operating Unit
0 39 31
S Source 2
0
Ignored
MAC
S
39 31
Destination 0
10
Figure 3.16 Fixed-Point Multiply Operation Flow
Table 3.25 Variation of Fixed-Point Multiply Operation
Mnemonic
PMULS
Function
Signed multiplication
Source 1
Se
Source 2
Sf
Destination
Dg
Table 3.26 Correspondence between Operands and Registers
Register
Se
Sf
Dg
A0
—
—
Yes
A1
Yes
Yes
Yes
M0
—
—
Yes
M1
—
—
Yes
X0
Yes
Yes
—
X1
Yes
—
—
Y0
Yes
Yes
—
Y1
—
Yes
—
Note: The multiply operations basically generate 32-bit operation results. So when a register
providing the guard-bit parts are specified as a destination operand, the guard-bit parts will
copy bit 31 of the operation result.
The multiply operation of the DSP unit side is not integer but fixed-point arithmetic. So, the upper
words of each multiplier and multiplicand are input into a MAC unit as shown in figure 3.16. In
the SH's standard multiply operations, the lower words of both source operands are input into a
MAC unit. The operation result is also different from the SH's case. The SH's multiply operation
Rev. 2.00 Dec. 07, 2005 Page 127 of 950
REJ09B0079-0200