SH7710 Datasheet, PDF (717/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
Initial
Bit
Bit Name Value R/W Description
6
RBSY1 0
R/W MAC-1 Overflow Alert Signal Output
Set to 1 when the threshold of TSU_BSYSL1 is valid
and exceeded
5

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
4
RINT51 0
R/W MAC-1 Residual Bit Frame Receive
Set to 1 when frames containing residual bits (less than
an 8-bit unit) are received in the MAC-1
3
RINT41 0
R/W MAC-1 Exceeding Byte Frame Receive
Set to 1 when frames exceeding the value set by
RFLR1 are received in the MAC-1
2
RINT31 0
R/W MAC-1 Less 64-Byte Frame Receive
Set to 1 when frames with a length of less than 64
bytes are received in the MAC-1
1
RINT21 0
R/W MAC-1 Frame Receive Error
Set to 1 when a receive error is detected on the RX-ER
pin input from the PHY in the MAC-1
0
RINT11 0
R/W MAC-1 CRC Error Frame Receive
Set to 1 when a receive frame results in a CRC error in
the MAC-1
18.3.35 Relay Status Interrupt Mask Register (TSU_FWINMK)
TSU_FWINMK is a 32-bit readable/writable register that sets the interrupt mask for status bits in
TSU_FWSR.
Initial
Bit
Bit Name Value
31 to 28 
All 0
27
TINTM40 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W MAC-0 Carrier Not Detect Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
Rev. 2.00 Dec. 07, 2005 Page 675 of 950
REJ09B0079-0200