SH7710 Datasheet, PDF (512/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
7 to 3 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
2
AE
0
R/(W)* Address Error Flag
Indicates that an address error occurred by the DMAC.
When this bit is set, DMA transfer is disabled even if the
DE bit in CHCR and the DME bit in DMAOR are set to 1.
This bit can only be cleared by writing 0 after reading 1.
0: No DMAC address error
1: DMAC address error
[Clear conditions]
Writing 0 after reading 1 from this bit
1
NMIF
0
R/(W)* NMI Flag
Indicates that an NMI interrupt occurred. When this bit is
set, DMA transfer is disabled even if the DE bit in CHCR
and the DME bit in DMAOR are set to 1. This bit can only
be cleared by writing 0 after reading 1.
When the NMI is input, the DMA transfer in progress can
be done in one transfer unit. Even if the DMAC is not in
operational, this bit is set to 1 when the NMI interrupt was
input.
0: No NMI interrupt
1: NMI interrupt occurs
[Clearing conditions]
Writing 0 after reading 1 from this bit
0
DME
0
R/W DMA Master Enable
Enables or disables DMA transfers on all channels. If the
DME bit and the DE bit in CHCR are set to 1, DMA
transfer is enabled. Note that transfer is enabled if the TE
bit in CHCR and the NMIF and AE bits in DMAOR are all
0. If this bit is cleared, DMA transfers in all the channels
can be terminated.
0: Disables DMA transfers on all channels
1: Enables DMA transfers on all channels
Note: * Only 0 can be written to clear the flag.
Rev. 2.00 Dec. 07, 2005 Page 470 of 950
REJ09B0079-0200