SH7710 Datasheet, PDF (683/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3 Register Descriptions
The EtherC has the following registers. The last number of the abbreviation of the MAC layer
interface control register corresponds to the number of the two MAC layer interfaces (MAC-0 or
MAC-1). Some numbers have been omitted in the text. For details on addresses and access sizes
of registers, see section 24, List of Registers.
Reset Register:
• Software reset register (ARSTR)
MAC Layer Interface Control Registers:
Port 0
• EtherC mode register (ECMR0)
• EtherC status register (ECSR0)
• EtherC interrupt permission register (ECSIPR0)
• PHY interface register (PIR0)
• MAC address high register (MAHR0)
• MAC address low register (MALR0)
• Receive frame length register (RFLR0)
• PHY status register (PSR0)
• Transmit retry over counter register (TROCR0)
• Delayed collision detect counter register (CDCR0)
• Lost carrier counter register (LCCR0)
• Carrier not detect counter register (CNDCR0)
• CRC error frame receive counter register (CEFCR0)
• Frame receive error counter register (FRECR0)
• Too-short frame receive counter register (TSFRCR0)
• Too-long frame receive counter register (TLFRCR0)
• Residual-bit frame receive counter register (RFCR0)
• Multicast address frame receive counter register (MAFCR0)
• IPG register (IPGR0)
Rev. 2.00 Dec. 07, 2005 Page 641 of 950
REJ09B0079-0200