SH7710 Datasheet, PDF (34/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 25.9 PLL Synchronization Settling Time by Reset or NMI ............................................ 863
Figure 25.10 PLL Synchronization Settling Time by IRQ/IRL Interrupts ................................. 864
Figure 25.11 PLL Synchronization Settling Time when Frequency Multiplication
Ratio Modified...................................................................................................... 864
Figure 25.12 Reset Input Timing................................................................................................ 866
Figure 25.13 Interrupt Signal Input Timing................................................................................ 866
Figure 25.14 Bus Release Timing .............................................................................................. 866
Figure 25.15 Pin Drive Timing at Standby................................................................................. 867
Figure 25.16 IRQOUT Output Delay Time................................................................................ 867
Figure 25.17 Basic Bus Cycle (No Wait) ................................................................................... 870
Figure 25.18 Basic Bus Cycle (One Software Wait) .................................................................. 871
Figure 25.19 Basic Bus Cycle (One External Wait) ................................................................... 872
Figure 25.20 Basic Bus Cycle (One Software Wait, External Wait Enabled (WM bit = 0),
No Idle Cycle Setting) .......................................................................................... 873
Figure 25.21 Burst ROM Read Cycle (One Access Wait, One External Wait,
One Burst Wait, Two Bursts)................................................................................ 874
Figure 25.22 Synchronous DRAM Single Read Bus Cycle (Auto Precharge,
CAS Latency = 2, TRCD = 1 Cycle, TRP = 1 Cycle)........................................... 875
Figure 25.23 Synchronous DRAM Single Read Bus Cycle (Auto Precharge,
CAS Latency = 2, TRCD = 2 Cycle, TRP = 2 Cycle)........................................... 876
Figure 25.24 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4),
(Auto Precharge, CAS Latency = 2, TRCD = 1 Cycle, TRP = 2 Cycle)............... 877
Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4),
(Auto Precharge, CAS Latency = 2, TRCD = 2 Cycle, TRP = 1 Cycle)............... 878
Figure 25.26 Synchronous DRAM Single Write Bus Cycle (Auto Precharge,
TRWL = 2 Cycle) ................................................................................................. 879
Figure 25.27 Synchronous DRAM Single Write Bus Cycle (Auto Precharge,
TRCD = 3 Cycle, TRWL = 2 Cycle) .................................................................... 880
Figure 25.28 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4),
(Auto Precharge, TRCD = 1 Cycle, TRWL = 2 Cycle) ........................................ 881
Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4),
(Auto Precharge, TRCD = 2 Cycle, TRWL = 2 Cycle) ........................................ 882
Figure 25.30 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode, ACTV + READ Commands, CAS Latency = 2,
TRCD = 1 Cycle) .................................................................................................. 883
Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode, READ Command, Same Row Address, CAS Latency = 2,
TRCD = 1 Cycle) .................................................................................................. 884
Rev. 2.00 Dec. 07, 2005 Page xxxiv of xlii