SH7710 Datasheet, PDF (237/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Memory Management Unit (MMU)
5.3.2 TLB Indexing
The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16
to 12 are used as the index number regardless of the page size. The index number can be generated
in two different ways depending on the setting of the IX bit in MMUCR.
1. When IX = 0, VPN bits 16 to 12 alone are used as the index number
2. When IX = 1, VPN bits 16 to 12 are EX-ORed with ASID bits 4 to 0 to generate a 5-bit index
number
The first method is used to prevent lowered TLB efficiency that results when multiple processes
run simultaneously in the same virtual address space (multiple virtual memory) and a specific
entry is selected by indexing of each process. In single virtual memory mode (MMUCR.SV = 1),
IX bit should be set to 0. Figures 5.8 and 5.9 show the indexing schemes.
Virtual Address
31
17 16 12 11
Index
PTEH Register
0
31
10 7
0
VPN
0 ASID
Exclusive-OR
ASID(4-0)
Way 0 to 3
0 VPN(31-17) VPN(11-10) ASID(7-0) V PPN(28-10) PR(1-0) SZ C D SH
31
Address Array
Data Array
Figure 5.8 TLB Indexing (IX = 1)
Rev. 2.00 Dec. 07, 2005 Page 195 of 950
REJ09B0079-0200