SH7710 Datasheet, PDF (982/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
Page Revision (See Manual for Details)
19.2 Register Descriptions
729 Deleted
• Receive data padding insert register (RPADIR0)
• Receive data padding insert register (RPADIR1)
19.2.2 E-DMAC Transmit Request 731
Register (EDTRR)
If the TACT bit of a transmit descriptor is cleared to 0
(invalid), the E-DMAC clears the TR bit and stops
transmit DMAC operation.
For details of writing to the TR bit, see section 19.4.1,
Using of EDTRR and EDRRR.
19.2.3 E-DMAC Receive Request 732
Register (EDRRR)
If the RACT bit of the receive descriptor is cleared to 0
(invalid), the E-DMAC clears the RR bit and stops
receive DMAC operation.
For details of writing to the RR bit, see section 19.4.1,
Using of EDTRR and EDRRR.
Rev. 2.00 Dec. 07, 2005 Page 940 of 950
REJ09B0079-0200