SH7710 Datasheet, PDF (345/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Power-Down Modes
• Canceling with a Reset
Sleep mode is canceled by a power-on reset or a manual reset.
10.3.2 Software Standby Mode
Transition to Software Standby Mode: The LSI switches from a program execution state to a
software standby mode by executing the SLEEP instruction when the STBY bit is 1 in STBCR. In
a software standby mode, not only the CPU but also the clock and on-chip peripheral modules
halt. The clock output from the CKIO pin also halts.
The contents of the CPU and cache registers remain unchanged. Some registers of on-chip
peripheral modules are, however, initialized. Table 10.3 lists the states of on-chip peripheral
modules registers in software standby mode.
Table 10.3 Register States in Software Standby Mode
Module
Interrupt Controller (INTC)
On-Chip Oscillation Circuits
User Break Controller (UBC)
Bus State Controller (BSC)
Timer Unit (TMU)
IPSEC
I/O ports
H-UDI
SCIF0/1
SIOF0/1
EtherC, E-DMAC
DMAC
Registers Initialized
—
—
—
—
TSTR
—
—
—
—
—
—
—
Registers Retaining Data
All registers
All registers
All registers
All registers
Registers other than TSTR
All registers
All registers
All registers
All registers
All registers
All registers
All registers
Rev. 2.00 Dec. 07, 2005 Page 303 of 950
REJ09B0079-0200