SH7710 Datasheet, PDF (278/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
IRQOUT
NMI
IRL3 to IRL0
IRQ5 to IRQ0
DMAC
SCIF0/1
E-DMAC
IPSEC
SIOF0/1
TMU
RTC
WDT
REF
H-UDI
Input/output
4
control
8
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Priority
identifier
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICRn
IPRn
IRRn
Bus
interface
Interrupt controller
[Legend]
DMAC: Direct memory access controller
SCIF0/1: Serial communication interface with FIFO
E-DMAC: Direct memory access controller for ethernet controller
IPSEC: IP security accelerator
SIOF0/1: Serial I/O with FIFO
TMU: Timer unit
RTC: Realtime clock unit
WDT: Watchdog timer
REF: Refresh request in bus state controller
H-UDI: User-debugging interface
ICRn: Interrupt control registers 0, 1
IPRn: Interrupt priority registers A to I
IRRn: Interrupt request registers 0 to 5, 7 and 8
SR:
Status register
Figure 8.1 Block Diagram of INTC
Rev. 2.00 Dec. 07, 2005 Page 236 of 950
REJ09B0079-0200