SH7710 Datasheet, PDF (15/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

5.6.2 Data Array ............................................................................................................ 211
5.6.3 Usage Examples.................................................................................................... 213
5.7 Usage Note......................................................................................................................... 213
Section 6 Cache .................................................................................................215
6.1 Features.............................................................................................................................. 215
6.1.1 Cache Structure..................................................................................................... 215
6.2 Register Descriptions ......................................................................................................... 217
6.2.1 Cache Control Register 1 (CCR1) ........................................................................ 217
6.2.2 Cache Control Register 2 (CCR2) ........................................................................ 218
6.2.3 Cache Control Register 3 (CCR3) ........................................................................ 221
6.3 Operation ........................................................................................................................... 222
6.3.1 Searching the Cache.............................................................................................. 222
6.3.2 Read Access.......................................................................................................... 223
6.3.3 Prefetch Operation ................................................................................................ 224
6.3.4 Write Access ......................................................................................................... 224
6.3.5 Write-Back Buffer ................................................................................................ 224
6.3.6 Coherency of Cache and External Memory .......................................................... 225
6.4 Memory-Mapped Cache .................................................................................................... 226
6.4.1 Address Array ....................................................................................................... 226
6.4.2 Data Array ............................................................................................................ 227
6.4.3 Usage Examples.................................................................................................... 230
Section 7 X/Y Memory......................................................................................231
7.1 Features.............................................................................................................................. 231
7.2 Operation ........................................................................................................................... 232
7.2.1 Access from CPU.................................................................................................. 232
7.2.2 Access from DSP .................................................................................................. 232
7.2.3 Access from DMAC, E-DMAC, and IPSEC ........................................................ 233
7.3 Usage Notes ....................................................................................................................... 233
7.3.1 Page Conflict ........................................................................................................ 233
7.3.2 Bus Conflict .......................................................................................................... 233
7.3.3 MMU and Cache Settings..................................................................................... 233
7.3.4 Sleep Mode ........................................................................................................... 234
7.3.5 Address Error........................................................................................................ 234
Section 8 Interrupt Controller (INTC) ...............................................................235
8.1 Features.............................................................................................................................. 235
8.1.1 Block Diagram...................................................................................................... 235
8.2 Input/Output Pins ............................................................................................................... 237
Rev. 2.00 Dec. 07, 2005 Page xv of xlii