SH7710 Datasheet, PDF (581/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
4
O/E
0
R/W Parity Mode
Selects either even or odd parity for use in parity
addition and checking. The O/E bit setting is only
valid when the PE bit is set to 1, enabling parity bit
addition and checking in asynchronous mode. The
O/E bit setting is invalid in clock synchronous mode,
and when parity addition and checking is disabled in
asynchronous mode.
0: Even parity*¹
1: Odd parity*²
Notes: 1. When even parity is set, parity bit addition
is performed in transmission so that the
total number of 1-bits in the transmit
character plus the parity bit is even. In
reception, a check is performed to see if
the total number of 1-bits in the receive
character plus the parity bit is even.
2. When odd parity is set, parity bit addition
is performed in transmission so that the
total number of 1-bits in the transmit
character plus the parity bit is odd. In
reception, a check is performed to see if
the total number of 1-bits in the receive
character plus the parity bit is odd.
Rev. 2.00 Dec. 07, 2005 Page 539 of 950
REJ09B0079-0200