SH7710 Datasheet, PDF (394/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
1
HW1
0
R/W Number of Delay Cycles from RD, WEn (BEn) negation to
0
HW0
0
R/W ^{Address, CSn negation}
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS2WCR, CS3WCR
Bit
31 to
21
Initial
Bit Name Value R/W

All 0 R
20
BAS
0
R/W
19 to 
11
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
and asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn (BEn) signal during the read/write
access cycle and asserts the RD/WR signal at the write
timing.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Dec. 07, 2005 Page 352 of 950
REJ09B0079-0200