SH7710 Datasheet, PDF (722/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.37 Added Qtag Value Set Register (Port 1 to 0) (TSU_ADQT1)
TSU_ADQT1 sets Qtag data to be added in the conversion of normal Ethernet frames (without
Qtag) to IEEE802.1Q frames (with Qtag) in port 1 to 0 relay operations (when setting the
QTAGM11 to QTAGM10 bits in TSU_QTAGM1 to H′3 in the use of the Qtag addition function).
Writing to this register is prohibited, after relay operations have been enabled once (after the
FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1).
Initial
Bit
Bit Name Value
31 to 16 QTAG131 to H′8100
QTAG116
15 to 13 QTAG115 to H′0
QTAG113
12

0
11 to 0 QTAG111 to H′000
QTAG100
R/W Description
R/W Be sure to set the value of the upper 16 bits
(QTAG131 to QTAG116) as H′8100 (indicates that it
is the Qtag extension frame format). The value read
is H′8100.
R/W Priority Setting (PRT)
These bits set the processing priority of frames with
Qtag. For details on the settings, refer to the
specifications on Qtag control specified in
IEEE802.1Q.
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W V-LAN ID Setting (VID)
These bits set the flames with Qtag to be used in the
systems supporting V-LAN. For details on settings,
refer to the specifications on Qtag control specified in
IEEE802.1Q.
Rev. 2.00 Dec. 07, 2005 Page 680 of 950
REJ09B0079-0200