SH7710 Datasheet, PDF(681/996 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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SH7710 Datasheet, PDF (681/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Section 18 Ethernet Controller (EtherC)

18.2 Input/Output Pins

Table 18.1 lists the pin configuration of the EtherC.

Table 18.1 Pin Configuration

Name

Transmit clock

Port

0

Receive clock

0

Transmit enable 0

Transmit data

0

Transmit error

0

Receive data valid 0

Receive data

0

Receive error

0

Carrier detection 0

Collision detection 0

Management data 0

clock

Management data 0

I/O

Link status

0

General-purpose 0

external output

Wake-On-LAN

0

Transmit clock

1

Receive clock

1

Abbreviation I/O

TX-CLK0*1 I

RX-CLK0*1 I

TX-EN0*1

O

ETXD03 to O

ETXD00*1

TX-ER0*1

O

RX-DV0*1 I

ERXD03 to I

ERXD00*1

RX-ER0*1 I

CRS0*1

I

COL0*1

I

MDC0*1

O

MDIO0*1

I/O

LNKSTA0 I

EXOUT0

O

WOL0

O

TX-CLK1*1 I

RX-CLK1*1 I

Function

TX-EN, ETXD3 to ETXD0, TX-ER timing

reference signal

RX-DV, ERXD3 to ERXD0, RX-ER timing

reference signal

Indicates that transmit data is ready on

ETXD3 to ETXD0

4-bit transmit data

Notifies PHY_LSI of error during

transmission

Indicates that valid receive data is on

ERXD3 to ERXD0

4-bit receive data

Identifies error state occurred during data

reception

Carrier detection signal

Collision detection signal

Reference clock signal for information

transfer via MDIO

Bidirectional signal for exchange of

management information between this LSI

and PHY

Inputs link status from PHY

Signal indicating value of register-bit

(ECMR0-ELB)

Signal indicating reception of Magic Packet

TX-EN, ETXD3 to ETXD0, TX-ER timing

reference signal

RX-DV, ERXD3 to ERXD0, RX-ER timing

reference signal

Rev. 2.00 Dec. 07, 2005 Page 639 of 950

REJ09B0079-0200

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