SH7710 Datasheet, PDF (975/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
Page Revision (See Manual for Details)
12.4.3 CSn Space Wait Control 352
Register (CSnWCR) (n = 0, 2, 3, to
4, 5A, 5B, 6A, 6B)
361
Normal Space, Byte-Selection
SRAM:
• CS2WCR, CS3WCR
• CS4WCR
• CS5AWCR
• CS5BWCR
• CS6AWCR
Bit Bit Name Description
10 WR3
Number of Access Wait Cycles
9 WR2
8 WR1
7 WR0
Specify the number of wait cycles
that are necessary for read/write
access.
0000: 0 cycle
:
Burst ROM
(Clock Asynchronous):
• CS0WCR
• CS4WCR
363 Bit Bit Name Description
to
10 W3
365
9 W2
Number of Access Wait Cycles
Specify the number of wait cycles
8 W1
7 W0
to be inserted in the first read/write
access cycle.
:
SDRAM*
• CS2WCR
367
Bit
Initial
Bit Name Value R/W Description
31 to 
11
All 0 R
Reserved
These bits are always read as 0.
The write value should always be 0.
10 
1
R
Reserved
These bits are always read as 1.
The write value should always be 1.
9

0
R
Reserved
These bits are always read as 0.
The write value should always be 0.
8
A2CL1 1
R/W CAS Latency for Area 2
7
A2CL0 0
R/W Specify the CAS latency for area 2.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Rev. 2.00 Dec. 07, 2005 Page 933 of 950
REJ09B0079-0200