SH7710 Datasheet, PDF (96/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Type
Branch
instructions
System
control
instructions
Total:
Kinds of
Instruction
9
Op Code
BF
BT
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
15
CLRT
CLRMAC
CLRS
LDC
LDS
LDTLB
NOP
PREF
RTE
SETS
SETT
SLEEP
STC
STS
TRAPA
68
Function
Conditional branch, delayed
conditional branch (T = 0)
Conditional branch, delayed
conditional branch (T = 1)
Unconditional branch
Unconditional branch
Branch to subroutine procedure
Branch to subroutine procedure
Unconditional branch
Branch to subroutine procedure
Return from subroutine procedure
T bit clear
MAC register clear
S bit clear
Load into control register
Load into system register
PTEH/PTEL load into TLB
No operation
Data prefetch to cache
Return from exception handling
S bit setting
T bit setting
Transition to power-down mode
Store from control register
Store from system register
Trap exception handling
Number of
Instructions
11
75
188
The instruction code, operation, and number of execution states of the CPU instructions are shown
in the following tables, classified by instruction type, using the format shown below.
Rev. 2.00 Dec. 07, 2005 Page 54 of 950
REJ09B0079-0200