SH7710 Datasheet, PDF (685/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
• Relay status register (TSU_FWSR)
• Relay status interrupt mask register (TSU_FWINMK)
• Added Qtag value set register (port 0 to 1) (TSU_ADQT0)
• Added Qtag value set register (port 1 to 0) (TSU_ADQT1)
• CAM entry table busy register (TSU_ADSBSY)
• CAM entry table enable register (TSU_TEN)
• CAM entry table POST1 to POST4 registers (TSU_POST1 to TSU_POST4)
• CAM entry table 0 to 31 H registers (TSU_ADRH0 to TSU_ADRH31)
• CAM entry table 0 to 31 L registers (TSU_ADRL0 to TSU_ADRL31)
• Transmit frame counter register (port 0) (normal transmission only) (TXNLCR0)
• Transmit frame counter register (port 0) (normal and error transmission) (TXALCR0)
• Receive frame counter register (port 0) (normal reception only) (RXNLCR0)
• Receive frame counter register (port 0) (normal and error reception) (RXALCR0)
• Relay frame counter register (port 1 to 0) (normal relay only) (FWNLCR0)
• Relay frame counter register (port 1 to 0) (normal and error relay) (FWALCR0)
• Transmit frame counter register (port 1) (normal transmission only) (TXNLCR1)
• Transmit frame counter register (port 1) (normal and error transmission) (TXALCR1)
• Receive frame counter register (port 1) (normal reception only) (RXNLCR1)
• Receive frame counter register (port 1) (normal and error reception) (RXALCR1)
• Relay frame counter register (port 0 to 1) (normal relay only) (FWNLCR1)
• Relay frame counter register (port 0 to 1) (normal and error relay) (FWALCR1)
Rev. 2.00 Dec. 07, 2005 Page 643 of 950
REJ09B0079-0200