SH7710 Datasheet, PDF (709/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Initial
Bit
Bit Name Value R/W
7 to 0 
All 0
R
Section 18 Ethernet Controller (EtherC)
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
18.3.30 Receive/Relay Function Set Register (Port 1 to 0) (TSU_FWSL1)
TSU_FWSL1 sets the processing method of each frame in port 1 reception and port 1 to 0 relay
operations. In receiving a frame, the processing method can be determined by referring to the
CAM evaluation results when the multicast frame and the destination are other than this LSI. (For
details, refer to section 18.4.4, CAM Function.) Writing to this register is prohibited, after relay
operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in
TSU_FWEN1 is set to 1).
Initial
Bit
Bit Name Value R/W
31 to 12 
All 0
R
11
FW41
0
R/W
10
FW31
0
R/W
9
FW21
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Sets the processing method when frames from port 1
are addressed to this LSI
0: Frames are not relayed
1: Frames are relayed to port 0
Sets the processing method when frames from port 1
are Broadcast.
0: Frames are not relayed
1: Frames are relayed to port 0
Sets the processing method when frames from port 1
are multicast.
0: CAM hit: Frames are relayed to port 0
CAM mishit: Frames are not relayed
1: CAM hit: Frames are not relayed
CAM mishit: Frames are relayed to port 0
Rev. 2.00 Dec. 07, 2005 Page 667 of 950
REJ09B0079-0200