SH7710 Datasheet, PDF (741/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.45 CAM Entry Table 0 to 31 L Registers (TSU_ADRL0 to TSU_ADRL31)
TSU_ADRL0 to TSU_ADRL31 are entry tables referred by the CAM in reception and relay. This
register sets the lower 16 bits of the 48-bit MAC address. Maximum 32 entries of MAC addresses
can be registered. To refer to input signals on the CAMSEN0 and CAMSEN 1 pins, do not set the
same MAC address set by this register to the entry tables of the external CAM.
Initial
Bit
Bit Name Value
R/W Description
31 to 16 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
15 to 0 ADRLn15 to All 0
ADRLn0
(n: 0 to 31)
R/W MAC Address Bit
These bits set the lower 16 bits of the MAC address.
When the MAC address is 01-23-45-67-89-AB
(displayed in hexadecimal), H′000089AB is set to this
register.
Notes: Set the CAM entry table as follows:
1. Check that the ADSBSY bit in TSU_ADSBSY is cleared to 0.
2. Set the upper 32 bits of the MAC address by TSU_ADRH0 to TSU_ADRH31.
3. Set the lower 16 bits of the MAC address by TSU_ADRL0 to TSU_ADRL31.
18.3.46 Transmit Frame Counter Register (Port 0) (Normal Transmission Only)
(TXNLCR0)
TXNLCR0 is a 32-bit counter indicating the number of frames successfully transmitted in MAC-
0. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is
cleared to 0 by a read to this register. This register cannot be written.
Bit
Bit Name Initial Value R/W
31 to 0 NTC031 to All 0
R
NTC000
Description
Port 0 Transmit Frame Counter Bit
These bits indicate the number of frames
successfully transmitted.
Rev. 2.00 Dec. 07, 2005 Page 699 of 950
REJ09B0079-0200