SH7710 Datasheet, PDF (766/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
This LSI
EtherC
TSU
802.1Q supporting
network
Frame conversion
mechanism
Qtag deleting
Qtag adding
802.1Q unsupporting
network
802.1Q conforming frame
(With Qtag)
MAC-0
MAC-1
Normal frame (Without Qtag)
Figure 18.11 Diagram of Qtag Additional Functions
Normal Ethernet frame
7 oct 1 oct
6 oct
PR SFD
DA
6 oct
SA
(Without Qtag)
2 oct
L/T
46 to 1500 oct
Data
4 oct
FCS
802.1Q conforming frame
7 oct 1oct
6 oct
PR SFD
DA
6 oct
SA
(With Qtag)
4 oct 2 oct
Qtag L/T
42 to 1500 oct
Data
4 oct
FCS
8 bit 8 bit
H'81
H'00
3 bit 1 bit
PRT CFI
12 bit
VID
Legend:
Extension code
PR: PReamble
(Fixed)
SFD: Start Frame Delimiter
DA: Destination Address
SA: Source Address
L/T: Length or Type
FCS: Frame Check Sequence
Qtag setting (TSU_ADQT0/1)
PRT: Priority level setting
CFI: Fixed at 0
VID: V-LAN ID setting
Figure 18.12 Comparison of Normal Ethernet Frame and IEEE802.1Q Frame (with Qtag)
Rev. 2.00 Dec. 07, 2005 Page 724 of 950
REJ09B0079-0200