SH7710 Datasheet, PDF (463/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
then when precharging is completed, the access is performed by issuing an ACTV command
followed by a READ or WRIT command. If this is followed by an access to a different row
address, the access time will be longer because of the precharging performed after the access
request is issued. The number of cycles between issuance of the PRE command and the ACTV
command is determined by the TRP[1:0] bits in CSnWCR.
In a write, when an auto-precharge is performed, a command cannot be issued to the same bank
for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode
is used, READ or WRIT commands can be issued successively if the row address is the same. The
number of cycles can thus be reduced by Trwl + Tap cycles for each write.
There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee
that there will not be a cache hit and another row address will be accessed within the period in
which this value is maintained by program execution, it is necessary to set auto-refresh and set the
refresh cycle to no more than the maximum value of tRAS.
A burst read cycle without auto-precharge is shown in figure 12.19, a burst read cycle for the same
row address in figure 12.20, and a burst read cycle for different row addresses in figure 12.21.
Similarly, a single write cycle without auto-precharge is shown in figure 12.22, a single write
cycle for the same row address in figure 12.23, and a single write cycle for different row addresses
in figure 12.24.
In figure 12.20, a Tnop cycle in which no operation is performed is inserted before the Tc cycle
that issues the READ command. The Tnop cycle is inserted to acquire two cycles of CAS latency
for the DQMxx signal that specifies the read byte in the data read from the SDRAM. If the CAS
latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of
latency can be acquired even if the DQMxx signal is asserted after the Tc cycle.
When bank active mode is set, if only accesses to the respective banks in the area 3 space are
considered, as long as accesses to the same row address continue, the operation starts with the
cycle in figure 12.19 or 12.22, followed by repetition of the cycle in figure 12.20 or 12.23. An
access to a different area during this time has no effect. If there is an access to a different row
address in the bank active state, after this is detected the bus cycle in figure 12.21 or 12.24 is
executed instead of that in figure 12.20 or 12.23. In bank active mode, too, all banks become
inactive after a refresh cycle or after the bus is released as the result of bus arbitration.
Rev. 2.00 Dec. 07, 2005 Page 421 of 950
REJ09B0079-0200