SH7710 Datasheet, PDF (168/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
operation result. The definition of the DC bit is selected by the CS[2:0] (condition selection) bits
in DSR. The DC bit result is:
Carry or Borrow Mode: CS[2:0] = 000: The DC bit is always cleared.
Negative Value Mode: CS[2:0] = 001: Bit 31 of the operation result is loaded into the DC bit.
Zero Value Mode: CS[2:0] = 010: The DC bit is set when the operation result is zero; otherwise
it is cleared.
Overflow Mode: CS[2:0] = 011: The DC bit is always cleared.
Signed Greater Than Mode: CS[2:0] = 100: The DC bit is always cleared.
Signed Greater Than or Equal Mode: CS[2:0] = 101: The DC bit is always cleared.
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
3.5.7 Fixed-Point Multiply Operation
Figure 3.16 shows the multiply operation flow. Table 3.25 shows the variation of this type of
operation and table 3.26 shows the correspondence between each operand and registers. The
multiply operation of the DSP unit is single-word signed single-precision multiplication. These
operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same
stage as the MA stage in which memory access is performed.
If a double-precision multiply operation is needed, the CPU standard double-word multiply
instructions can be made of use.
Rev. 2.00 Dec. 07, 2005 Page 126 of 950
REJ09B0079-0200