SH7710 Datasheet, PDF(41/996 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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SH7710 Datasheet, PDF (41/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Table 16.2

Table 16.3

Table 16.4

Table 16.5

Table 16.6

Relationship between n and Clock........................................................................ 553

SCSMR Settings for Serial Transfer Format Selection......................................... 560

SCSMR and SCSCR Settings for the SCIF Clock Source Selection .................... 560

Serial Transfer Formats......................................................................................... 562

The SCIF Interrupt Sources .................................................................................. 583

Section 17 Serial I/O with FIFO (SIOF)

Table 17.1 Pin Configuration.................................................................................................. 589

Table 17.2 SIOF Serial Clock Frequency ............................................................................... 614

Table 17.3 Serial Transfer Modes........................................................................................... 616

Table 17.4 Frame Length........................................................................................................ 617

Table 17.5 Audio Mode Specification for Transmit Data....................................................... 619

Table 17.6 Audio Mode Specification for Receive Data ........................................................ 619

Table 17.7 Setting for Number of Control Data Channels...................................................... 620

Table 17.8 Conditions to Issue Transmit Request .................................................................. 622

Table 17.9 Conditions to Issue Receive Request .................................................................... 622

Table 17.10 Transmission and Reception Reset ....................................................................... 628

Table 17.11 SIOF Interrupt Sources ......................................................................................... 629

Table 17.12 Setting Condition of Transmit/Receive Interrupt Flag.......................................... 630

Section 18 Ethernet Controller (EtherC)

Table 18.1 Pin Configuration.................................................................................................. 639

Table 18.2 Transfer Frame Processing (Without CAM)......................................................... 711

Table 18.3 Reception Frame Process...................................................................................... 713

Table 18.4 Relay Frame Process (With CAM) ....................................................................... 713

Table 18.5 Receive Frame Process (When External CAM Logic is Used)............................. 715

Table 18.6 Relay Frame Process (When External CAM Logic is Used) ................................ 716

Section 21 Pin Function Controller (PFC)

Table 21.1 List of Multiplexed Pins (1).................................................................................. 781

Table 21.2 List of Multiplexed Pins (2).................................................................................. 782

Section 22 I/O Ports

Table 22.1 Port A Data Register (PADR) Read/Write Operations ......................................... 790

Table 22.2 Port B Data Register (PBDR) Read/Write Operations (1) .................................... 791

Table 22.3 Port B Data Register (PBDR) Read/Write Operations (2) .................................... 791

Table 22.4 Port C Data Register (PCDR) Read/Write Operations.......................................... 792

Section 23 User Debugging Interface (H-UDI)

Table 23.1 Pin Configuration.................................................................................................. 794

Table 23.2 H-UDI Commands................................................................................................ 796

Table 23.3 This LSIâs Pins and Boundary Scan Register Bits................................................ 797

Table 23.4 Reset Configuration .............................................................................................. 805

Rev. 2.00 Dec. 07, 2005 Page xli of xlii

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