SH7710 Datasheet, PDF (448/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 bits) 01 (12 bits) 10 (10 bits)
Output Pin of Row Address Column Address Synchronous
This LSI
Output
Output
DRAM Pin
Function
A2
A12
A2
A0
A1
A11
A1
Unused
A0
A10
A0
Example of connected memory
512-Mbit product (4 Mwords x 32 bits x 4 banks, column 10 bits
product): 1
256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10 bits
product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev. 2.00 Dec. 07, 2005 Page 406 of 950
REJ09B0079-0200