SH7710 Datasheet, PDF (725/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
Initial
Bit
Bit Name Value R/W Description
24
TEN7
0
R/W CAM Entry Table 7 (TSU_ADRH7 and TSU_ADRL7)
Setting
0: Disabled
1: Enabled
23
TEN8
0
R/W CAM Entry Table 8 (TSU_ADRH8 and TSU_ADRL8)
Setting
0: Disabled
1: Enabled
22
TEN9
0
R/W CAM Entry Table 9 (TSU_ADRH9 and TSU_ADRL9)
Setting
0: Disabled
1: Enabled
21
TEN10 0
R/W CAM Entry Table 10 (TSU_ADRH10 and TSU_ADRL10)
Setting
0: Disabled
1: Enabled
20
TEN11 0
R/W CAM Entry Table 11 (TSU_ADRH11 and TSU_ADRL11)
Setting
0: Disabled
1: Enabled
19
TEN12 0
R/W CAM Entry Table 12 (TSU_ADRH12 and TSU_ADRL12)
Setting
0: Disabled
1: Enabled
18
TEN13 0
R/W CAM Entry Table 13 (TSU_ADRH13 and TSU_ADRL13)
Setting
0: Disabled
1: Enabled
17
TEN14 0
R/W CAM Entry Table 14 (TSU_ADRH14and TSU_ADRL14)
Setting
0: Disabled
1: Enabled
Rev. 2.00 Dec. 07, 2005 Page 683 of 950
REJ09B0079-0200